Overview
D/AVE is a Hardware IP Core, optimized for easy integration into FPGAs and ASICs. Focus of D/AVE is to provide a high quality vector graphics with subpixel processing and an extended antialiasing functionality. The Hardware IP Core D/AVE contains an innovative rendering engine as main component which allows flexible system integration.
D/AVE has been developed for all applications that benefit from high quality vector graphics. Examples are Navigation, Dashboard and OSD Applications in the Automotive and Aviation area.
Feature highlights:
• High Quality Antialiasing
• Subpixel accurate rendering
• Resolutions up to 2048x2048
• Extended Rendering Primitives supported in Hardware
- LINES with arbitrary width, round and truncated endpoints, alpha
gradients, soft edges
- POLYGONS, triangles and quadrangles with support of alpha gradients,
soft edges and per edge control for antialiasing
- CIRCLES and ELLIPSES, support of all conic sections, filled or with
arbitrary width, arcs of 0°-360°, soft edges, alpha gradients
- QUADRATIC and CUBIC BÉZIER’S (Attribute: Color) support of arbitrary
width, round or truncated endpoints, alpha gradients
- Block Image Tranfers (BLIT)
• 16 Blending Modes
• Patterns and Gradients with Alpha Channel on all Primitives
• Textures up to 2048x1024
- Bilinear Filtering
- Render to Texture
- Texture Blending
• No Cost Hardware Clipping
• Flexible Input and Output Formats for Framebuffer and Textures
• Very Small Core Size
• Easy Core Integration
• Fully Reentrant Driver
Scope of Delivery & Requirements
The D/AVE 2D core is available in two different versions. A ‘standard’ version named D/AVE 2D-TS and ‘light’ version named D/AVE 2D-TL. The major differences between both cores are that D/AVE 2D-TL is not supporting performance counting and is slower in terms of pixel processing. The D/AVE 2D-TS render pipeline produces one pixel per cycle, D/AVE 2D-TL needs four cycles for a pixel.
In the ALTERA SOPC-Builder™ environment D/AVE uses Avalon bus interface, it is tested on the device families Cyclone II, Cyclone III and Stratix .An AMBA AHB/APB bus interface is also available.
• Quartus II 7.2
• NIOS II EDS 7.2
• Nios II Development Kit, Cyclone II Edition (2C35)
• Nios II Development Kit, Cyclone III FPGA Starter Kit (2C25)
Architecture
Contents of D/AVE EvalKit
• D/AVE 2D SOPC-Builder component v3.0, run-time limited
• Precompiled FPGA configurations (.sof files) for Altera Development Kits
• Precompiled demo applications for Altera Development Kits
• Example Quartus II projects for hardware integration of D/AVE
• Example Nios II IDE projects for software integration of D/AVE
• D/AVE API documentation
• Demo source code for showing usage of D/AVE API
• Nios II libraries of D/AVE driver V2.10
• Nios II sources of lowlevel driver V1.2
• Windows software emulation of D/AVE (SoftDAVE)
Example Screenshot
Related Links
